The present invention relates to a level shifter for converting the logic level and specifically to a level shifter which has a structure for achieving a low-voltage operation.
FIG. 25 is a circuit diagram showing a conventional level shifter.
The level shifter of FIG. 5 includes two N-type transistors N51 and N52, two P-type transistors P51 and P52 of cross-couple type wherein the gate of each transistor is connected to the drain of the other, and a first inverter INV50. The first inverter INV50 inverts an input signal from an input terminal IN and operates with lower voltage supply VDD of, e.g., 1.5 V. The elements other than the first inverter INV50 are higher voltage side elements which operate with higher voltage supply VDD3 of, e.g., 3.3 V. The two N-type transistors N51 and N52 have grounded sources and receive signals complementary to each other, i.e., the signal from the input terminal IN and the inverse of the input signal from the first inverter INV50. The two P-type transistors P51 and P52 have sources connected to higher voltage supply VDD3, gates cross-coupled to drains of each other, and drains connected to the drains of the N-type transistors N51 and N52, respectively. The connection point of the P-type transistor P51 and the N-type transistor N51 is a node W51, and the connection point of the P-type transistor P52 and the N-type transistor N52 is a node W52. The node W52 is connected to an output terminal OUT.
Next, an operation of the above level shifter is described. In a stationary state, for example, if the input signal is at H (VDD) level and the inverse thereof is at L (VSS=0 V) level, the N-type transistor N51 is ON, the N-type transistor N52 is OFF, the P-type transistor P51 is OFF, and the P-type transistor P52 is ON. The node W51 is at L (VSS) level, and the node W52 is at H (VDD3) level. Since the N-type transistor N51 and the P-type transistor P51 are complementary to each other and the N-type transistor N52 and the P-type transistor P52 are also complementary to each other, no current flows during this stationary state.
Thereafter, the input signal transitions to L (VSS) level. At the time of the state transition, the N-type transistor N51 is turned OFF, and the N-type transistor N52 is turned ON. Therefore, a through current flows from higher voltage supply VDD3 to the ground via the P-type transistor P52 and the N-type transistor N52 which are ON, so that the potential of the node W52 starts decreasing from H (VDD3) level. When the potential of the node W52 falls on or below VDD3-Vtp (Vtp is the threshold voltage of the P-type transistor P52), the P-type transistor P51 starts being turned ON, and the potential of the node W51 (the potential at the gate of the P-type transistor P52) increases, so that the drain current of the P-type transistor P52 decreases, and the potential of the node W52 further decreases.
Finally, the potential of the node W51 is at H (VDD3) level, and the potential of the node W52 at L (VSS) level, so that no through current flows and the output logic is inverted. Then, the operation waits for a next change in the input signal. Although the example where the input signal transitions from H (VDD) level to L (VSS) level has been described herein, the same applies to the inverse case.
In the above structure, when lower voltage supply VDD is as low as near the threshold voltage of the N-type transistors N51 and N52, the drain currents of the N-type transistors N51 and N52, which are necessary for decreasing the potentials of the nodes W51 and W52, are decreased. If the decreased drain currents are far smaller than the drain currents of the P-type transistors P51 and P52 which occur when they are ON, the potentials of the cross-coupled gates of the P-type transistors P51 and P52 cannot be decreased, so that the level shifter would not operate in some cases.
In view of such, conventionally, in the N-type transistors N51 and N52, the gate width is increased or the threshold voltage is lowered in order to increase the drain current during a period when they are ON, while in the P-type transistors P51 and P52 the gate width is decreased or the gate length is increased in order to decrease the drain current (i.e., in order to increase the ON resistance value) during a period when they are ON.
However, in the above-described conventional level shifter, if the ON resistance value of the P-type transistors P51 and P52 is increased to achieve a low-voltage operation, the drain currents of the P-type transistors P51 and P52 become small at the time of increasing the potentials of the nodes W51 and W52, and as a result, a high-speed operation cannot be achieved.
Conventionally, to overcome such a problem, Japanese Laid-Open Patent Publication No. 2002-76881 has proposed a level shifter wherein each of the nodes W51 and W52 is divided into a node whose potential is quickly decreased and a node whose potential is quickly increased. This level shifter is shown in FIG. 26. The level shifter of FIG. 26 includes, in addition to the components of FIG. 25, a resistor R51 between the node W51 and the gate of the P-type transistor P52 and a resistor R52 between the node W52 and the gate of the P-type transistor P51. The level shifter further includes a node W53 at the connection point of the resistor R51 and the gate of the P-type transistor P52, an N-type transistor N53 between the node W53 and the ground, a node W54 at the connection point of the resistor R52 and the gate of the P-type transistor P51, and an N-type transistor N54 between the node W54 and the ground. The gates of the N-type transistors N51 and N53 are connected to the input terminal IN. The gates of the N-type transistors N52 and N54 are connected to the output of the inverter INV50.
In the level shifter of FIG. 26, for example, when the input signal is at H (VDD) level, the N-type transistors N51 and N53 are ON, the N-type transistors N52 and N54 are OFF, the nodes W51 and W53 are at L (VSS) level, the P-type transistor P52 is ON, the nodes W52 and W54 are at H (VDD3) level, and the P-type transistor P51 is OFF. At the time of a state transition from this state to the state where the input signal falls from H (VDD) level to L (VSS) level, the N-type transistors N51 and N53 are turned OFF so that the nodes W51 and W53 are disconnected from the ground, while the N-type transistors N52 and N54 are turned ON so that the nodes W52 and W54 are connected to the ground and the potentials thereof start decreasing. On this occasion, if the resistor R52 has been set to have a large resistance value and the P-type transistor P52 has been set to have a small ON resistance value during a period when it is ON, the node W54 is connected with higher voltage supply VDD3 via the resistor R52 having high resistance value, and the potential of the node W54 falls to L (VSS) level more quickly than the potential of the node W52. Further, the P-type transistor PS1 is turned ON so that the potential of the node W51 increases more quickly. Furthermore, the gate of the P-type transistor P52 transitions to H (VDD3) level through the resistor R51 so that the P-type transistor P52 is turned OFF, whereby the potential of the node W52 is decreased to L (VSS) level. Although the example where the input signal transitions from H (VDD) level to L (VSS) level has been described herein, the same applies to the inverse case.
To enable the level shifter to operate at a lower voltage, it is effective, for the same reasons as those previously described for the level shifter of FIG. 25, that the resistors R51 and R52 are set to have a large resistance value and that the N-type transistors N53 and N54 are set to have a large gate width or a low threshold voltage such that the drain currents become large during a period when they are ON.
Conventionally, Japanese Laid-Open Patent Publication No. 2001-298356 has proposed a level shifter wherein a current is interrupted according to the potentials of the nodes W51 and W52. The structure of this level shifter is shown in FIG. 27.
The level shifter of FIG. 27 includes, in addition to the components of FIG. 25, P-type transistors P53 and P54 for current interruption between higher voltage supply VDD3 and the P-type transistors P51 and P52, respectively. The level shifter further includes a delay circuit D51 through which the potential of the node W51 is applied to the gate of the P-type transistor P53 and a delay circuit D52 through which the potential of the node W52 is applied to the gate of the P-type transistor P54. The connection point of the P-type transistors P51 and P53 is a node W55. The connection point of the P-type transistors P52 and P54 is a node W56. The level shifter further includes a pull-up resistor R53 between the nodes W55 and W56 for preventing the nodes W51 and W52 from floating.
In the above-described conventional level shifter having the current interruption function, for example, when the input signal is at H level, the N-type transistor N51 is ON, the N-type transistor N52 is OFF, the node W51 is at L (VSS) level, the node W52 is at H (VDD3) level, the P-type transistors P51 and P54 are OFF, and the P-type transistors P52 and P53 are ON. In this case, the node W52 is pulled up to higher voltage supply VDD3 by the P-type transistor P52, the resistor R53 having a large resistance value, and the P-type transistor P53. At the time of a state transition from this state to the state where the input signal falls to L (VSS) level, the N-type transistor N51 is turned OFF so that the node W51 is disconnected from the ground, while the N-type transistor N52 is turned ON so that the node W52 is connected to the ground and the potential thereof decreases. This change in potential is transferred to the P-type transistor P54, but the transfer is delayed by the delay circuit D52 by a predetermined time. During the predetermined delay time, the P-type transistor P51 is turned ON due to the decrease in potential at the node W52 so that higher voltage supply VDD3 and the node W51 are connected through the P-type transistors P51 and P53. Accordingly, the potential of the node W51 increases so that the P-type transistor P52 is turned OFF. Then, after the predetermined delay time generated by the delay circuit D52 due to the decrease in potential at the node W52, the P-type transistor P54 is turned ON. The increase in potential at the node W51 causes the P-type transistor P53 to be turned OFF after the predetermined delay time generated by the delay circuit D51. As a result, the node W51 is pulled up to higher voltage supply VDD3 by the P-type transistor P51, the resistor R53, and the P-type transistor P54, thereby being prevented from floating. Although the example where the input signal transitions from H (VDD) level to L (VSS) level has been described herein, the same applies to the inverse case.
To enable the level shifter to operate at a lower voltage, it is effective, for the same reasons as those previously described for the level shifter of FIG. 25, that the resistor R53 is set to have a large resistance value and that the N-type transistors N51 and N52 are set to have a large gate width or a low threshold voltage such that the drain current becomes large during a period when they are ON.
Japanese Laid-Open Patent Publication No. 2002-76882 has proposed a level shifter wherein changes in potential at the nodes W51 and W52 are detected for precharge control. The structure of this level shifter is shown in FIG. 28.
The level shifter of FIG. 28 includes, in addition to the components of FIG. 25, N-type transistors N55 and N56 between the ground and the N-type transistors N51 and N52, respectively. Instead of cross-coupling the gates of the P-type transistors P51 and P52, the gate of the N-type transistor N55 is connected to the gate of the P-type transistor P51, and the gate of the N-type transistor N56 is connected to the gate of the P-type transistor P52, whereby the nodes W51 and W52 are precharged, respectively. The level shifter further includes NAND circuits Nand51 and Nand52 and inverters INV51 and INV52. The NAND circuit Nand51 receives output signals of the node W51 and the NAND circuit Nand52. The NAND circuit Nand52 receives output signals of the node W52 and the NAND circuit Nand51. The inverter INV51 receives the output signal of the NAND circuit Nand51 and has an output terminal connected to the gate of the P-type transistor P51 and the gate of the N-type transistor N55. The inverter INV52 receives the output signal of the NAND circuit Nand52 and has an output terminal connected to the gate of the P-type transistor P52 and the gate of the N-type transistor N56. With this structure, detection of decreases in potential at the nodes W51 and W52 and a precharge operation are controlled. The level shifter further includes a pull-up resistor R54 between the nodes W51 and W52 for preventing the nodes W51 and W52 from floating. The output terminal OUT is connected to the output of the NAND circuit Nand52 instead of the node W52.
In the above-described conventional level shifter having the precharge control function, for example, when the input signal is at H (VDD) level, the nodes W51 and W52 are both at H (VDD3) level, the output of the NAND circuit Nand51 is at H (VDD3) level, the output of the NAND circuit Nand52 is at L (VSS) level, and a flip flop circuit formed by the NAND circuits Nand51 and Nand52 holds the output logic. In this case, the output of the inverter INV51 is at L (VSS) level, and the output of the inverter INV52 is at H (VDD3) level. Therefore, the P-type transistor P51 is ON so that the node W51 is connected to higher voltage supply VDD3, while the N-type transistor N55 is OFF so that the node W51 is disconnected from the ground, whereby the node W51 is precharged to a potential equal to higher voltage supply VDD3. Meanwhile, the P-type transistor P52 is OFF so that the node W52 is disconnected from the ground, while the N-type transistor N56 is ON so that the N-type transistor N52 is connected to the ground, whereby the node W52 is pulled up to higher voltage supply VDD3 by the resistor R54 having a large resistance value and the P-type transistor P51.
At the time of a state transition from this state to the state where the input signal falls to L (VSS) level, the N-type transistor N51 is turned OFF while the N-type transistor N52 is turned ON so that the node W52 is connected to the ground and the potential thereof decreases. When the potential of the node W52 falls below the switching level of the NAND circuit Nand52, the output of the NAND circuit Nand52 is inverted to H (VDD3) level, and the output of the NAND circuit Nand51 is inverted to L (VSS) level, so that the output logic at the output terminal OUT is inverted. The output logic of the inverter INV51 is inverted to H (VDD3) level, and the output logic of the inverter INV52 is inverted to L (VSS) level, so that the N-type transistor N56 is turned OFF, whereby the node W52 is disconnected from the ground. Meanwhile, the P-type transistor P52 is turned ON so that the node W52 is connected to higher voltage supply VDD3, whereby the node W52 is precharged to a potential equal to higher voltage supply VDD3. As for the precharged node W51, the P-type transistor P51 is turned OFF while the N-type transistor N55 is turned ON so that the N-type transistor N51 is connected to the ground, whereby the node W51 is pulled up to higher voltage supply VDD3 by the resistor R54 and the P-type transistor P52. Then, the operation waits for a next change in the input signal. Although the example where the input signal transitions from H (VDD) level to L (VSS) level has been described herein, the same applies to the inverse case.
To enable the level shifter to operate at a lower voltage, it is effective, for the same reasons as those previously described for the level shifter of FIG. 25, that the resistor R54 is set to have a large resistance value and that the N-type transistors N51 and N52 are set to have a large gate width or a low threshold voltage such that the drain currents become large during a period when they are ON.
However, in the level shifter of FIG. 25, if the P-type transistors P51 and P52 are set to have a large ON resistance value such that the level shifter operates even when lower voltage supply VDD is further lowered, the connection resistance of the node W51 or W52 which is currently connected to higher voltage supply VDD3 becomes large during a stationary state where the potential of the node W51 or W52 is at H (VDD3) level. Thus, even if the corresponding N-type transistor N51 or N52 for signal input is OFF, the potential of the node W51 or W52 is lower than a potential equal to higher voltage supply VDD3 due to an OFF leakage current flowing therethrough. If, alternatively, the N-type transistors N51 and N52 for signal input are set to have a lower threshold voltage such that the level shifter operates even when lower voltage supply VDD is further lowered, the OFF leakage current increases accordingly during a period when the N-type transistor N51 or N52 is OFF, and the decrease in potential from higher voltage supply VDD3, which occurs when the node W51 or W52 is at H (VDD3) level, becomes greater. If this potential decrease level becomes greater than the threshold voltage of the P-type transistor P51 or P52, the P-type transistor P51 or P52 cannot be turned OFF, so that the level shifter can cause a malfunction. Furthermore, in the N-type transistors N51 and N52 for signal input, the OFF leakage current increases even when the threshold voltage is decreased due to a variation in temperature or production process thereof, thereby inhibiting the normal operation.
In the level shifter of FIG. 26, if the resistors R51 and R52 are set to have a large resistance value such that the level shifter operates even when lower voltage supply VDD is further lowered, the connection resistance of the node W53 or W54 which is currently connected to higher voltage supply VDD3 becomes large during a stationary state where the potential of the node W53 or W54 is at H (VDD3) level. Thus, even if the corresponding N-type transistor N53 or N54 for signal input is OFF, the potential of the node W53 or W54 is lower than a potential equal to higher voltage supply VDD3 due to an OFF leakage current flowing therethrough. If, alternatively, the N-type transistor N53 and N54 for signal input are set to have a lower threshold voltage such that the level shifter operates even when lower voltage supply VDD is further lowered, the OFF leakage current increases accordingly during a period when the N-type transistor N53 or N54 is OFF, and the decrease in potential from higher voltage supply VDD3, which occurs when the node W53 or W54 is at H (VDD3) level, becomes greater. If this potential decrease level becomes greater than the threshold voltage of the P-type transistor PS1 or P52, the P-type transistor P51 or P52 cannot be turned OFF, so that the level shifter can cause a malfunction. Furthermore, in the N-type transistors N53 and N54 for signal input, the OFF leakage current increases even when the threshold voltage is decreased due to a variation in temperature or production process thereof, thereby inhibiting the normal operation.
In the level shifter of FIG. 27, if the resistor R53 is set to have a large resistance value such that the level shifter operates even when lower voltage supply VDD is further lowered, the connection resistance of the node W51 or W52 which is currently connected to higher voltage supply VDD3 becomes large during a stationary state where the potential of the node W51 or W52 are at H (VDD3) level. Thus, even if the corresponding N-type transistor N51 or N52 for signal input is OFF, the potential of the node W51 or W52 is lower than a potential equal to higher voltage supply VDD3 due to an OFF leakage current flowing therethrough. If, alternatively, the N-type transistor N51 and N52 for signal input are set to have a lower threshold voltage such that the level shifter operates even when lower voltage supply VDD is further lowered, the OFF leakage current increases accordingly during a period when the N-type transistor N51 or N52 is OFF, and the decrease in potential from higher voltage supply VDD3, which occurs when the node W51 or W52 is at H (VDD3) level, becomes greater. If this potential decrease level becomes greater than the threshold voltage of the P-type transistor P51 or P52, the P-type transistor P51 or P52 cannot be turned OFF, so that the level shifter can cause a malfunction. Furthermore, in the N-type transistors N51 and N52 for signal input, the OFF leakage current increases even when the threshold voltage is decreased due to a variation in temperature or production process thereof, thereby inhibiting the normal operation.
In the level shifter of FIG. 28, if the resistor R54 is set to have a large resistance value such that the level shifter operates even when lower voltage supply VDD is further lowered, the connection resistance of the node W51 or W52 which is currently pulled up to higher voltage supply VDD3 by the resistor R54 becomes large during a stationary state where the node W51 or W52 is pulled up to H (VDD3) level. Thus, even if the corresponding N-type transistor N51 or N52 for signal input is OFF, the potential of the node W51 or W52 is lower than a potential equal to higher voltage supply VDD3 due to an OFF leakage current flowing therethrough. If, alternatively, the N-type transistors N51 and N52 for signal input are set to have a lower threshold voltage such that the level shifter operates even when lower voltage supply VDD is further lowered, the OFF leakage current increases accordingly during a period when the N-type transistor N51 or N52 is OFF, and the decrease in potential from higher voltage supply VDD3, which occurs when the node W51 or W52 is at H (VDD3) level, becomes greater. If this potential falls below the threshold voltage of the NAND circuits Nand51 and NandS2, the level shifter can cause a malfunction. Furthermore, in the N-type transistors N51 and N52 for signal input, the OFF leakage current increases even when the threshold voltage is decreased due to a variation in temperature or production process thereof, thereby inhibiting the normal operation.